(1) Field of the Invention
This invention relates, in general, to the construction of programmable read only memories (PROMs) by integrated circuit techniques utilizing short circuiting of PN junctions.
(2) Description of the Prior Art
Matrix arrays in which information is permanently located are known in the art. The matrix array comprises rows and columns of parallel electrical conductors having back-to-back diodes or a transistor connecting the intersections, or cross over points, of the rows and columns and the entire matrix is formed as a single integrated circuit. After the manufacture of the circuit, at predetermined intersections of the rows and columns, the connector devices are permanently altered through the application of a voltage across one of the junctions of the diodes or the transistors thus forming a Read-Only-Memory (ROM). Examples of such permanently altered matrix arrays utilizing transistors and back-to-back PN junctions or diodes at the intersection of the rows and columns of conductors are shown in the U.S. Pats. Nos. 3,742,592, 3,848,238 and 3,733,690. These patents also teach methods for applying suitable current to selected conductors to program the Read-Only-Memory to form a PROM by fusing or shorting the desired PN junctions at the selected conductor cross-over points. These back-to-back PN junctions also require excessive energy to fuse the junctions which is time consuming. The problem involved in this prior art was (and still is) to make certain that the desired PN junction of the selected pair of junctions in the transistor or pair of diodes is the one that is shorted so that a programming error is not introduced into the PROM. Because of this problem, considerable time and carefully monitored voltages were utilized to prevent such an error. For example, the foregoing Rizzi U.S. Pat. No. 3,742,592 teaches the need for careful regulation of an applied pulse current of a predetermined amplitude and duration across the junctions by carefully limiting not only the pulse height but also the pulse width taking into consideration the parameters involved in the structure of the junction. Another patent in this field is the U.S. Pat. No. 3,641,516 to Castrucci et al, which also shows back-to-back diodes, or "cells" as they are referred to in the patent, in an integrated circuit matrix wherein selected diodes of the cells are fused, or permanently altered, by directing a fusing current to the selected diodes in the cells. This patent was directed towards avoiding a so-called "sneak path" problem by making the diodes in a cell such that the diodes to be fused have a lower breakdown voltage than those which are not to be fused. This was accomplished by providing an N+ region formed in the epitaxial layer between two P regions and touching one of the P regions. The patent also discloses the use of free metal which is not connected to other conductor elements of the chip to provide a terminal for an aluminum-silicon alloy connection across the fused junction formed by the fusing process. This patent further describes in some detail the amount of power and the length of time that is required to fuse the junctions. For example, it stated that the device having the free metal and the N+ region " . . . was found to fuse (in this case to go from 8 volts to less than 1 volt) in about 1 to 10 milliseconds under an applied current of 100 milliampers . . . " Column 4 lines 60-63. When fusion took place, an aluminum-silicon alloy connector formed beneath the oxide coating and connected the conductor of the row or column to the free metal thus shorting the PN+ junction.
Thus, all of the prior art recognize the need for ensuring that the selected junction of a pair of back-to-back diodes, or of a transistor, is fused to make the desired connection between the selected row and column conductors of the matrix and also the problem of excess energy consumption.
When the energy required to fuse the selected junction is great, the programming of a matrix is slow because the entire chip would be destroyed by heat unless the matrix is programmed slowly cell by cell. Today, the programming of the matrix is done on a maschine which applies the correct pattern of pulses and could apply such pulses in a few microseconds except that the speed of the programming process is too fast so much heat is generated that there is a danger of destroying the entire chip. Thus, a relatively expensive machine capable of high speed operation is operated at a relatively low speed.
Another factor in the matter of excess energy to program the devices is that other transistors on the chip must be extra large to supply or control this energy without destruction. This extra size limits the number of devices that can be placed on the chip. This size requirement necessitates a larger circuit path which causes the circuitry to operate slower not at the time of programming the matrix but when the information stored in the memory is read out.
Turning now again to the foregoing prior art, it is apparent that it did not address the correct solution of the error reduction problem and excess energy consumption.
More specifically, the prior art did not recognize that a reduction in energy is related inversely to the distance from the PN junction to that free metal and thus the location of the free metal on the chip as well as the size of the free metal is important for the reduction of power and time more so than simply providing a terminal for an aluminum-silicon alloy connection and also presumably as a supplier of aluminum atoms for formation of the aluminum-silicon alloy as set forth in the Castrucci et al, patent, supra. The reason that size is important is that it has been discovered that this properly located piece of free metal, if kept as small as possible, will avoid excess absorption of heat and serves to localize the heat, otherwise conducted away, involved in the fusion process and thus reduces the power consumption.
Accordingly, from the foregoing, it can be seen that one of the objects to this invention is to reduce energy in programming a PROM and at the same time reduce programming errors which have occurred in the prior art PROMs.